@@ -415,24 +415,20 @@ void vdp_dump_registers(const VDP *vdp) | |||||
return; | return; | ||||
DEBUG("Dumping PNT:") | DEBUG("Dumping PNT:") | ||||
for (uint16_t i = 0; i < 28 * 32; i += 32) { | |||||
uint16_t w[32]; | |||||
for (uint8_t j = 0; j < 32; j++) | |||||
w[j] = vdp->vram[get_pnt_base(vdp) + 2 * (i + j)] + | |||||
(vdp->vram[get_pnt_base(vdp) + 2 * (i + j) + 1] << 8); | |||||
DEBUG("- %03X %03X %03X %03X %03X %03X %03X %03X" | |||||
" %03X %03X %03X %03X %03X %03X %03X %03X" | |||||
" %03X %03X %03X %03X %03X %03X %03X %03X" | |||||
" %03X %03X %03X %03X %03X %03X %03X %03X", | |||||
w[0x00], w[0x01], w[0x02], w[0x03], w[0x04], w[0x05], w[0x06], w[0x07], | |||||
w[0x08], w[0x09], w[0x0A], w[0x0B], w[0x0C], w[0x0D], w[0x0E], w[0x0F], | |||||
w[0x10], w[0x11], w[0x12], w[0x13], w[0x14], w[0x15], w[0x16], w[0x17], | |||||
w[0x18], w[0x19], w[0x1A], w[0x1B], w[0x1C], w[0x1D], w[0x1E], w[0x1F]) | |||||
for (uint16_t i = 0; i < 18; i++) { | |||||
uint16_t w[20]; | |||||
for (uint8_t j = 0; j < 20; j++) | |||||
w[j] = get_background_tile(vdp, i + 3, j + 6); | |||||
DEBUG("- %03X %03X %03X %03X %03X %03X %03X %03X %03X %03X" | |||||
" %03X %03X %03X %03X %03X %03X %03X %03X %03X %03X", | |||||
w[0x00], w[0x01], w[0x02], w[0x03], w[0x04], w[0x05], w[0x06], | |||||
w[0x07], w[0x08], w[0x09], w[0x0A], w[0x0B], w[0x0C], w[0x0D], | |||||
w[0x0E], w[0x0F], w[0x10], w[0x11], w[0x12], w[0x13]) | |||||
} | } | ||||
DEBUG("Dumping PGT:") | DEBUG("Dumping PGT:") | ||||
for (uint16_t i = 0; i < /* 512 */ 16; i++) { | |||||
for (uint16_t i = 0; i < /* 512 */ 32; i++) { | |||||
uint32_t w[8]; | uint32_t w[8]; | ||||
for (uint8_t j = 0; j < 8; j++) | for (uint8_t j = 0; j < 8; j++) | ||||
w[j] = vdp->vram[32 * i + 4 * j] + | w[j] = vdp->vram[32 * i + 4 * j] + | ||||
@@ -65,6 +65,7 @@ void z80_power(Z80 *z80) | |||||
z80->except = false; | z80->except = false; | ||||
z80->pending_cycles = 0; | z80->pending_cycles = 0; | ||||
z80->irq_wait = false; | |||||
z80->trace.fresh = true; | z80->trace.fresh = true; | ||||
z80->trace.last_addr = 0; | z80->trace.last_addr = 0; | ||||
@@ -231,7 +232,7 @@ static inline uint8_t get_interrupt_mode(const Z80 *z80) | |||||
/* | /* | ||||
Handle an active IRQ line. Return the number of cycles consumed. | Handle an active IRQ line. Return the number of cycles consumed. | ||||
*/ | */ | ||||
static inline uint8_t handle_interrupt(Z80 *z80) | |||||
static inline uint8_t accept_interrupt(Z80 *z80) | |||||
{ | { | ||||
TRACE("Z80 triggering mode-%d interrupt", get_interrupt_mode(z80)) | TRACE("Z80 triggering mode-%d interrupt", get_interrupt_mode(z80)) | ||||
z80->regs.iff1 = z80->regs.iff2 = 0; | z80->regs.iff1 = z80->regs.iff2 = 0; | ||||
@@ -298,10 +299,13 @@ bool z80_do_cycles(Z80 *z80, double cycles) | |||||
{ | { | ||||
cycles += z80->pending_cycles; | cycles += z80->pending_cycles; | ||||
while (cycles > 0 && !z80->except) { | while (cycles > 0 && !z80->except) { | ||||
if (io_check_irq(z80->io) && z80->regs.iff1) { | |||||
cycles -= handle_interrupt(z80); | |||||
if (io_check_irq(z80->io) && z80->regs.iff1 && !z80->irq_wait) { | |||||
cycles -= accept_interrupt(z80); | |||||
continue; | continue; | ||||
} | } | ||||
if (z80->irq_wait) | |||||
z80->irq_wait = false; | |||||
uint8_t opcode = mmu_read_byte(z80->mmu, z80->regs.pc); | uint8_t opcode = mmu_read_byte(z80->mmu, z80->regs.pc); | ||||
increment_refresh_counter(z80); | increment_refresh_counter(z80); | ||||
if (TRACE_LEVEL) | if (TRACE_LEVEL) | ||||
@@ -68,6 +68,7 @@ typedef struct { | |||||
bool except; | bool except; | ||||
uint8_t exc_code, exc_data; | uint8_t exc_code, exc_data; | ||||
double pending_cycles; | double pending_cycles; | ||||
bool irq_wait; | |||||
Z80TraceInfo trace; | Z80TraceInfo trace; | ||||
} Z80; | } Z80; | ||||
@@ -1182,6 +1182,7 @@ static uint8_t z80_inst_ei(Z80 *z80, uint8_t opcode) | |||||
(void) opcode; | (void) opcode; | ||||
z80->regs.iff1 = true; | z80->regs.iff1 = true; | ||||
z80->regs.iff2 = true; | z80->regs.iff2 = true; | ||||
z80->irq_wait = true; | |||||
z80->regs.pc++; | z80->regs.pc++; | ||||
return 4; | return 4; | ||||
} | } | ||||