2 changed files with 1137 additions and 13 deletions
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+613 -1src/assembler/instructions.inc.c
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+524 -12src/assembler/instructions.yml
+ 613
- 1
src/assembler/instructions.inc.c
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| @@ -7,7 +7,7 @@ | |||||
| `make` should trigger a rebuild when it is modified; if not, use: | `make` should trigger a rebuild when it is modified; if not, use: | ||||
| `python scripts/update_asm_instructions.py`. | `python scripts/update_asm_instructions.py`. | ||||
| @AUTOGEN_DATE Wed May 20 06:24:37 2015 UTC | |||||
| @AUTOGEN_DATE Wed May 20 06:40:09 2015 UTC | |||||
| */ | */ | ||||
| /* @AUTOGEN_INST_BLOCK_START */ | /* @AUTOGEN_INST_BLOCK_START */ | ||||
| @@ -1323,6 +1323,335 @@ INST_FUNC(outi) | |||||
| INST_RETURN(2, 0xED, 0xA3) | INST_RETURN(2, 0xED, 0xA3) | ||||
| } | } | ||||
| INST_FUNC(pop) | |||||
| { | |||||
| INST_TAKES_ARGS( | |||||
| AT_REGISTER, | |||||
| AT_NONE, | |||||
| AT_NONE | |||||
| ) | |||||
| if (INST_TYPE(0) == AT_REGISTER) { | |||||
| if (INST_REG(0) == REG_BC) | |||||
| INST_RETURN(1, 0xC1) | |||||
| if (INST_REG(0) == REG_DE) | |||||
| INST_RETURN(1, 0xD1) | |||||
| if (INST_REG(0) == REG_HL) | |||||
| INST_RETURN(1, 0xE1) | |||||
| if (INST_REG(0) == REG_IX) | |||||
| INST_RETURN(2, INST_IX_PREFIX, 0xE1) | |||||
| if (INST_REG(0) == REG_IY) | |||||
| INST_RETURN(2, INST_IY_PREFIX, 0xE1) | |||||
| if (INST_REG(0) == REG_AF) | |||||
| INST_RETURN(1, 0xF1) | |||||
| INST_ERROR(ARG_VALUE) | |||||
| } | |||||
| INST_ERROR(ARG_TYPE) | |||||
| } | |||||
| INST_FUNC(push) | |||||
| { | |||||
| INST_TAKES_ARGS( | |||||
| AT_REGISTER, | |||||
| AT_NONE, | |||||
| AT_NONE | |||||
| ) | |||||
| if (INST_TYPE(0) == AT_REGISTER) { | |||||
| if (INST_REG(0) == REG_BC) | |||||
| INST_RETURN(1, 0xC5) | |||||
| if (INST_REG(0) == REG_DE) | |||||
| INST_RETURN(1, 0xD5) | |||||
| if (INST_REG(0) == REG_HL) | |||||
| INST_RETURN(1, 0xE5) | |||||
| if (INST_REG(0) == REG_IX) | |||||
| INST_RETURN(2, INST_IX_PREFIX, 0xE5) | |||||
| if (INST_REG(0) == REG_IY) | |||||
| INST_RETURN(2, INST_IY_PREFIX, 0xE5) | |||||
| if (INST_REG(0) == REG_AF) | |||||
| INST_RETURN(1, 0xF5) | |||||
| INST_ERROR(ARG_VALUE) | |||||
| } | |||||
| INST_ERROR(ARG_TYPE) | |||||
| } | |||||
| INST_FUNC(res) | |||||
| { | |||||
| INST_TAKES_ARGS( | |||||
| AT_IMMEDIATE, | |||||
| AT_INDEXED|AT_INDIRECT|AT_REGISTER, | |||||
| AT_OPTIONAL|AT_REGISTER | |||||
| ) | |||||
| if (INST_NARGS == 2 && INST_TYPE(0) == AT_IMMEDIATE && INST_TYPE(1) == AT_REGISTER) { | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 0) && INST_REG(1) == REG_A) | |||||
| INST_RETURN(2, 0xCB, 0x87) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 0) && INST_REG(1) == REG_B) | |||||
| INST_RETURN(2, 0xCB, 0x80) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 0) && INST_REG(1) == REG_C) | |||||
| INST_RETURN(2, 0xCB, 0x81) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 0) && INST_REG(1) == REG_D) | |||||
| INST_RETURN(2, 0xCB, 0x82) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 0) && INST_REG(1) == REG_E) | |||||
| INST_RETURN(2, 0xCB, 0x83) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 0) && INST_REG(1) == REG_H) | |||||
| INST_RETURN(2, 0xCB, 0x84) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 0) && INST_REG(1) == REG_L) | |||||
| INST_RETURN(2, 0xCB, 0x85) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 1) && INST_REG(1) == REG_A) | |||||
| INST_RETURN(2, 0xCB, 0x8F) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 1) && INST_REG(1) == REG_B) | |||||
| INST_RETURN(2, 0xCB, 0x88) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 1) && INST_REG(1) == REG_C) | |||||
| INST_RETURN(2, 0xCB, 0x89) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 1) && INST_REG(1) == REG_D) | |||||
| INST_RETURN(2, 0xCB, 0x8A) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 1) && INST_REG(1) == REG_E) | |||||
| INST_RETURN(2, 0xCB, 0x8B) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 1) && INST_REG(1) == REG_H) | |||||
| INST_RETURN(2, 0xCB, 0x8C) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 1) && INST_REG(1) == REG_L) | |||||
| INST_RETURN(2, 0xCB, 0x8D) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 2) && INST_REG(1) == REG_A) | |||||
| INST_RETURN(2, 0xCB, 0x97) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 2) && INST_REG(1) == REG_B) | |||||
| INST_RETURN(2, 0xCB, 0x90) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 2) && INST_REG(1) == REG_C) | |||||
| INST_RETURN(2, 0xCB, 0x91) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 2) && INST_REG(1) == REG_D) | |||||
| INST_RETURN(2, 0xCB, 0x92) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 2) && INST_REG(1) == REG_E) | |||||
| INST_RETURN(2, 0xCB, 0x93) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 2) && INST_REG(1) == REG_H) | |||||
| INST_RETURN(2, 0xCB, 0x94) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 2) && INST_REG(1) == REG_L) | |||||
| INST_RETURN(2, 0xCB, 0x95) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 3) && INST_REG(1) == REG_A) | |||||
| INST_RETURN(2, 0xCB, 0x9F) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 3) && INST_REG(1) == REG_B) | |||||
| INST_RETURN(2, 0xCB, 0x98) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 3) && INST_REG(1) == REG_C) | |||||
| INST_RETURN(2, 0xCB, 0x99) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 3) && INST_REG(1) == REG_D) | |||||
| INST_RETURN(2, 0xCB, 0x9A) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 3) && INST_REG(1) == REG_E) | |||||
| INST_RETURN(2, 0xCB, 0x9B) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 3) && INST_REG(1) == REG_H) | |||||
| INST_RETURN(2, 0xCB, 0x9C) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 3) && INST_REG(1) == REG_L) | |||||
| INST_RETURN(2, 0xCB, 0x9D) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 4) && INST_REG(1) == REG_A) | |||||
| INST_RETURN(2, 0xCB, 0xA7) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 4) && INST_REG(1) == REG_B) | |||||
| INST_RETURN(2, 0xCB, 0xA0) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 4) && INST_REG(1) == REG_C) | |||||
| INST_RETURN(2, 0xCB, 0xA1) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 4) && INST_REG(1) == REG_D) | |||||
| INST_RETURN(2, 0xCB, 0xA2) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 4) && INST_REG(1) == REG_E) | |||||
| INST_RETURN(2, 0xCB, 0xA3) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 4) && INST_REG(1) == REG_H) | |||||
| INST_RETURN(2, 0xCB, 0xA4) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 4) && INST_REG(1) == REG_L) | |||||
| INST_RETURN(2, 0xCB, 0xA5) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 5) && INST_REG(1) == REG_A) | |||||
| INST_RETURN(2, 0xCB, 0xAF) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 5) && INST_REG(1) == REG_B) | |||||
| INST_RETURN(2, 0xCB, 0xA8) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 5) && INST_REG(1) == REG_C) | |||||
| INST_RETURN(2, 0xCB, 0xA9) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 5) && INST_REG(1) == REG_D) | |||||
| INST_RETURN(2, 0xCB, 0xAA) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 5) && INST_REG(1) == REG_E) | |||||
| INST_RETURN(2, 0xCB, 0xAB) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 5) && INST_REG(1) == REG_H) | |||||
| INST_RETURN(2, 0xCB, 0xAC) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 5) && INST_REG(1) == REG_L) | |||||
| INST_RETURN(2, 0xCB, 0xAD) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 6) && INST_REG(1) == REG_A) | |||||
| INST_RETURN(2, 0xCB, 0xB7) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 6) && INST_REG(1) == REG_B) | |||||
| INST_RETURN(2, 0xCB, 0xB0) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 6) && INST_REG(1) == REG_C) | |||||
| INST_RETURN(2, 0xCB, 0xB1) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 6) && INST_REG(1) == REG_D) | |||||
| INST_RETURN(2, 0xCB, 0xB2) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 6) && INST_REG(1) == REG_E) | |||||
| INST_RETURN(2, 0xCB, 0xB3) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 6) && INST_REG(1) == REG_H) | |||||
| INST_RETURN(2, 0xCB, 0xB4) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 6) && INST_REG(1) == REG_L) | |||||
| INST_RETURN(2, 0xCB, 0xB5) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 7) && INST_REG(1) == REG_A) | |||||
| INST_RETURN(2, 0xCB, 0xBF) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 7) && INST_REG(1) == REG_B) | |||||
| INST_RETURN(2, 0xCB, 0xB8) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 7) && INST_REG(1) == REG_C) | |||||
| INST_RETURN(2, 0xCB, 0xB9) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 7) && INST_REG(1) == REG_D) | |||||
| INST_RETURN(2, 0xCB, 0xBA) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 7) && INST_REG(1) == REG_E) | |||||
| INST_RETURN(2, 0xCB, 0xBB) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 7) && INST_REG(1) == REG_H) | |||||
| INST_RETURN(2, 0xCB, 0xBC) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 7) && INST_REG(1) == REG_L) | |||||
| INST_RETURN(2, 0xCB, 0xBD) | |||||
| INST_ERROR(ARG_VALUE) | |||||
| } | |||||
| if (INST_NARGS == 2 && INST_TYPE(0) == AT_IMMEDIATE && INST_TYPE(1) == AT_INDIRECT && | |||||
| (INST_INDIRECT(1).type == AT_REGISTER && INST_INDIRECT(1).addr.reg == REG_HL)) { | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 0)) | |||||
| INST_RETURN(2, 0xCB, 0x86) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 1)) | |||||
| INST_RETURN(2, 0xCB, 0x8E) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 2)) | |||||
| INST_RETURN(2, 0xCB, 0x96) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 3)) | |||||
| INST_RETURN(2, 0xCB, 0x9E) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 4)) | |||||
| INST_RETURN(2, 0xCB, 0xA6) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 5)) | |||||
| INST_RETURN(2, 0xCB, 0xAE) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 6)) | |||||
| INST_RETURN(2, 0xCB, 0xB6) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 7)) | |||||
| INST_RETURN(2, 0xCB, 0xBE) | |||||
| INST_ERROR(ARG_VALUE) | |||||
| } | |||||
| if (INST_NARGS == 2 && INST_TYPE(0) == AT_IMMEDIATE && INST_TYPE(1) == AT_INDEXED) { | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 0)) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0x86) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 1)) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0x8E) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 2)) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0x96) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 3)) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0x9E) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 4)) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xA6) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 5)) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xAE) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 6)) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xB6) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 7)) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xBE) | |||||
| INST_ERROR(ARG_VALUE) | |||||
| } | |||||
| if (INST_NARGS == 3 && INST_TYPE(0) == AT_IMMEDIATE && INST_TYPE(1) == AT_INDEXED && INST_TYPE(2) == AT_REGISTER) { | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 0) && INST_REG(2) == REG_A) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0x87) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 0) && INST_REG(2) == REG_B) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0x80) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 0) && INST_REG(2) == REG_C) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0x81) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 0) && INST_REG(2) == REG_D) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0x82) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 0) && INST_REG(2) == REG_E) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0x83) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 0) && INST_REG(2) == REG_H) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0x84) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 0) && INST_REG(2) == REG_L) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0x85) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 1) && INST_REG(2) == REG_A) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0x8F) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 1) && INST_REG(2) == REG_B) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0x88) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 1) && INST_REG(2) == REG_C) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0x89) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 1) && INST_REG(2) == REG_D) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0x8A) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 1) && INST_REG(2) == REG_E) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0x8B) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 1) && INST_REG(2) == REG_H) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0x8C) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 1) && INST_REG(2) == REG_L) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0x8D) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 2) && INST_REG(2) == REG_A) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0x97) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 2) && INST_REG(2) == REG_B) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0x90) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 2) && INST_REG(2) == REG_C) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0x91) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 2) && INST_REG(2) == REG_D) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0x92) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 2) && INST_REG(2) == REG_E) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0x93) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 2) && INST_REG(2) == REG_H) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0x94) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 2) && INST_REG(2) == REG_L) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0x95) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 3) && INST_REG(2) == REG_A) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0x9F) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 3) && INST_REG(2) == REG_B) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0x98) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 3) && INST_REG(2) == REG_C) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0x99) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 3) && INST_REG(2) == REG_D) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0x9A) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 3) && INST_REG(2) == REG_E) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0x9B) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 3) && INST_REG(2) == REG_H) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0x9C) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 3) && INST_REG(2) == REG_L) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0x9D) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 4) && INST_REG(2) == REG_A) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xA7) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 4) && INST_REG(2) == REG_B) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xA0) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 4) && INST_REG(2) == REG_C) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xA1) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 4) && INST_REG(2) == REG_D) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xA2) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 4) && INST_REG(2) == REG_E) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xA3) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 4) && INST_REG(2) == REG_H) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xA4) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 4) && INST_REG(2) == REG_L) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xA5) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 5) && INST_REG(2) == REG_A) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xAF) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 5) && INST_REG(2) == REG_B) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xA8) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 5) && INST_REG(2) == REG_C) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xA9) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 5) && INST_REG(2) == REG_D) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xAA) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 5) && INST_REG(2) == REG_E) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xAB) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 5) && INST_REG(2) == REG_H) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xAC) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 5) && INST_REG(2) == REG_L) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xAD) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 6) && INST_REG(2) == REG_A) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xB7) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 6) && INST_REG(2) == REG_B) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xB0) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 6) && INST_REG(2) == REG_C) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xB1) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 6) && INST_REG(2) == REG_D) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xB2) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 6) && INST_REG(2) == REG_E) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xB3) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 6) && INST_REG(2) == REG_H) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xB4) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 6) && INST_REG(2) == REG_L) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xB5) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 7) && INST_REG(2) == REG_A) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xBF) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 7) && INST_REG(2) == REG_B) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xB8) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 7) && INST_REG(2) == REG_C) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xB9) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 7) && INST_REG(2) == REG_D) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xBA) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 7) && INST_REG(2) == REG_E) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xBB) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 7) && INST_REG(2) == REG_H) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xBC) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 7) && INST_REG(2) == REG_L) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xBD) | |||||
| INST_ERROR(ARG_VALUE) | |||||
| } | |||||
| INST_ERROR(ARG_TYPE) | |||||
| } | |||||
| INST_FUNC(reti) | INST_FUNC(reti) | ||||
| { | { | ||||
| INST_TAKES_NO_ARGS | INST_TAKES_NO_ARGS | ||||
| @@ -1371,6 +1700,285 @@ INST_FUNC(scf) | |||||
| INST_RETURN(1, 0x37) | INST_RETURN(1, 0x37) | ||||
| } | } | ||||
| INST_FUNC(set) | |||||
| { | |||||
| INST_TAKES_ARGS( | |||||
| AT_IMMEDIATE, | |||||
| AT_INDEXED|AT_INDIRECT|AT_REGISTER, | |||||
| AT_OPTIONAL|AT_REGISTER | |||||
| ) | |||||
| if (INST_NARGS == 2 && INST_TYPE(0) == AT_IMMEDIATE && INST_TYPE(1) == AT_REGISTER) { | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 0) && INST_REG(1) == REG_A) | |||||
| INST_RETURN(2, 0xCB, 0xC7) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 0) && INST_REG(1) == REG_B) | |||||
| INST_RETURN(2, 0xCB, 0xC0) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 0) && INST_REG(1) == REG_C) | |||||
| INST_RETURN(2, 0xCB, 0xC1) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 0) && INST_REG(1) == REG_D) | |||||
| INST_RETURN(2, 0xCB, 0xC2) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 0) && INST_REG(1) == REG_E) | |||||
| INST_RETURN(2, 0xCB, 0xC3) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 0) && INST_REG(1) == REG_H) | |||||
| INST_RETURN(2, 0xCB, 0xC4) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 0) && INST_REG(1) == REG_L) | |||||
| INST_RETURN(2, 0xCB, 0xC5) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 1) && INST_REG(1) == REG_A) | |||||
| INST_RETURN(2, 0xCB, 0xCF) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 1) && INST_REG(1) == REG_B) | |||||
| INST_RETURN(2, 0xCB, 0xC8) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 1) && INST_REG(1) == REG_C) | |||||
| INST_RETURN(2, 0xCB, 0xC9) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 1) && INST_REG(1) == REG_D) | |||||
| INST_RETURN(2, 0xCB, 0xCA) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 1) && INST_REG(1) == REG_E) | |||||
| INST_RETURN(2, 0xCB, 0xCB) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 1) && INST_REG(1) == REG_H) | |||||
| INST_RETURN(2, 0xCB, 0xCC) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 1) && INST_REG(1) == REG_L) | |||||
| INST_RETURN(2, 0xCB, 0xCD) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 2) && INST_REG(1) == REG_A) | |||||
| INST_RETURN(2, 0xCB, 0xD7) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 2) && INST_REG(1) == REG_B) | |||||
| INST_RETURN(2, 0xCB, 0xD0) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 2) && INST_REG(1) == REG_C) | |||||
| INST_RETURN(2, 0xCB, 0xD1) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 2) && INST_REG(1) == REG_D) | |||||
| INST_RETURN(2, 0xCB, 0xD2) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 2) && INST_REG(1) == REG_E) | |||||
| INST_RETURN(2, 0xCB, 0xD3) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 2) && INST_REG(1) == REG_H) | |||||
| INST_RETURN(2, 0xCB, 0xD4) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 2) && INST_REG(1) == REG_L) | |||||
| INST_RETURN(2, 0xCB, 0xD5) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 3) && INST_REG(1) == REG_A) | |||||
| INST_RETURN(2, 0xCB, 0xDF) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 3) && INST_REG(1) == REG_B) | |||||
| INST_RETURN(2, 0xCB, 0xD8) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 3) && INST_REG(1) == REG_C) | |||||
| INST_RETURN(2, 0xCB, 0xD9) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 3) && INST_REG(1) == REG_D) | |||||
| INST_RETURN(2, 0xCB, 0xDA) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 3) && INST_REG(1) == REG_E) | |||||
| INST_RETURN(2, 0xCB, 0xDB) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 3) && INST_REG(1) == REG_H) | |||||
| INST_RETURN(2, 0xCB, 0xDC) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 3) && INST_REG(1) == REG_L) | |||||
| INST_RETURN(2, 0xCB, 0xDD) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 4) && INST_REG(1) == REG_A) | |||||
| INST_RETURN(2, 0xCB, 0xE7) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 4) && INST_REG(1) == REG_B) | |||||
| INST_RETURN(2, 0xCB, 0xE0) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 4) && INST_REG(1) == REG_C) | |||||
| INST_RETURN(2, 0xCB, 0xE1) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 4) && INST_REG(1) == REG_D) | |||||
| INST_RETURN(2, 0xCB, 0xE2) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 4) && INST_REG(1) == REG_E) | |||||
| INST_RETURN(2, 0xCB, 0xE3) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 4) && INST_REG(1) == REG_H) | |||||
| INST_RETURN(2, 0xCB, 0xE4) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 4) && INST_REG(1) == REG_L) | |||||
| INST_RETURN(2, 0xCB, 0xE5) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 5) && INST_REG(1) == REG_A) | |||||
| INST_RETURN(2, 0xCB, 0xEF) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 5) && INST_REG(1) == REG_B) | |||||
| INST_RETURN(2, 0xCB, 0xE8) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 5) && INST_REG(1) == REG_C) | |||||
| INST_RETURN(2, 0xCB, 0xE9) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 5) && INST_REG(1) == REG_D) | |||||
| INST_RETURN(2, 0xCB, 0xEA) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 5) && INST_REG(1) == REG_E) | |||||
| INST_RETURN(2, 0xCB, 0xEB) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 5) && INST_REG(1) == REG_H) | |||||
| INST_RETURN(2, 0xCB, 0xEC) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 5) && INST_REG(1) == REG_L) | |||||
| INST_RETURN(2, 0xCB, 0xED) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 6) && INST_REG(1) == REG_A) | |||||
| INST_RETURN(2, 0xCB, 0xF7) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 6) && INST_REG(1) == REG_B) | |||||
| INST_RETURN(2, 0xCB, 0xF0) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 6) && INST_REG(1) == REG_C) | |||||
| INST_RETURN(2, 0xCB, 0xF1) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 6) && INST_REG(1) == REG_D) | |||||
| INST_RETURN(2, 0xCB, 0xF2) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 6) && INST_REG(1) == REG_E) | |||||
| INST_RETURN(2, 0xCB, 0xF3) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 6) && INST_REG(1) == REG_H) | |||||
| INST_RETURN(2, 0xCB, 0xF4) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 6) && INST_REG(1) == REG_L) | |||||
| INST_RETURN(2, 0xCB, 0xF5) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 7) && INST_REG(1) == REG_A) | |||||
| INST_RETURN(2, 0xCB, 0xFF) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 7) && INST_REG(1) == REG_B) | |||||
| INST_RETURN(2, 0xCB, 0xF8) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 7) && INST_REG(1) == REG_C) | |||||
| INST_RETURN(2, 0xCB, 0xF9) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 7) && INST_REG(1) == REG_D) | |||||
| INST_RETURN(2, 0xCB, 0xFA) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 7) && INST_REG(1) == REG_E) | |||||
| INST_RETURN(2, 0xCB, 0xFB) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 7) && INST_REG(1) == REG_H) | |||||
| INST_RETURN(2, 0xCB, 0xFC) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 7) && INST_REG(1) == REG_L) | |||||
| INST_RETURN(2, 0xCB, 0xFD) | |||||
| INST_ERROR(ARG_VALUE) | |||||
| } | |||||
| if (INST_NARGS == 2 && INST_TYPE(0) == AT_IMMEDIATE && INST_TYPE(1) == AT_INDIRECT && | |||||
| (INST_INDIRECT(1).type == AT_REGISTER && INST_INDIRECT(1).addr.reg == REG_HL)) { | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 0)) | |||||
| INST_RETURN(2, 0xCB, 0xC6) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 1)) | |||||
| INST_RETURN(2, 0xCB, 0xCE) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 2)) | |||||
| INST_RETURN(2, 0xCB, 0xD6) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 3)) | |||||
| INST_RETURN(2, 0xCB, 0xDE) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 4)) | |||||
| INST_RETURN(2, 0xCB, 0xE6) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 5)) | |||||
| INST_RETURN(2, 0xCB, 0xEE) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 6)) | |||||
| INST_RETURN(2, 0xCB, 0xF6) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 7)) | |||||
| INST_RETURN(2, 0xCB, 0xFE) | |||||
| INST_ERROR(ARG_VALUE) | |||||
| } | |||||
| if (INST_NARGS == 2 && INST_TYPE(0) == AT_IMMEDIATE && INST_TYPE(1) == AT_INDEXED) { | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 0)) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xC6) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 1)) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xCE) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 2)) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xD6) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 3)) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xDE) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 4)) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xE6) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 5)) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xEE) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 6)) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xF6) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 7)) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xFE) | |||||
| INST_ERROR(ARG_VALUE) | |||||
| } | |||||
| if (INST_NARGS == 3 && INST_TYPE(0) == AT_IMMEDIATE && INST_TYPE(1) == AT_INDEXED && INST_TYPE(2) == AT_REGISTER) { | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 0) && INST_REG(2) == REG_A) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xC7) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 0) && INST_REG(2) == REG_B) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xC0) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 0) && INST_REG(2) == REG_C) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xC1) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 0) && INST_REG(2) == REG_D) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xC2) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 0) && INST_REG(2) == REG_E) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xC3) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 0) && INST_REG(2) == REG_H) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xC4) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 0) && INST_REG(2) == REG_L) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xC5) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 1) && INST_REG(2) == REG_A) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xCF) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 1) && INST_REG(2) == REG_B) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xC8) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 1) && INST_REG(2) == REG_C) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xC9) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 1) && INST_REG(2) == REG_D) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xCA) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 1) && INST_REG(2) == REG_E) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xCB) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 1) && INST_REG(2) == REG_H) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xCC) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 1) && INST_REG(2) == REG_L) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xCD) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 2) && INST_REG(2) == REG_A) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xD7) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 2) && INST_REG(2) == REG_B) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xD0) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 2) && INST_REG(2) == REG_C) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xD1) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 2) && INST_REG(2) == REG_D) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xD2) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 2) && INST_REG(2) == REG_E) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xD3) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 2) && INST_REG(2) == REG_H) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xD4) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 2) && INST_REG(2) == REG_L) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xD5) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 3) && INST_REG(2) == REG_A) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xDF) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 3) && INST_REG(2) == REG_B) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xD8) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 3) && INST_REG(2) == REG_C) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xD9) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 3) && INST_REG(2) == REG_D) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xDA) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 3) && INST_REG(2) == REG_E) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xDB) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 3) && INST_REG(2) == REG_H) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xDC) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 3) && INST_REG(2) == REG_L) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xDD) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 4) && INST_REG(2) == REG_A) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xE7) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 4) && INST_REG(2) == REG_B) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xE0) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 4) && INST_REG(2) == REG_C) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xE1) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 4) && INST_REG(2) == REG_D) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xE2) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 4) && INST_REG(2) == REG_E) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xE3) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 4) && INST_REG(2) == REG_H) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xE4) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 4) && INST_REG(2) == REG_L) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xE5) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 5) && INST_REG(2) == REG_A) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xEF) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 5) && INST_REG(2) == REG_B) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xE8) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 5) && INST_REG(2) == REG_C) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xE9) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 5) && INST_REG(2) == REG_D) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xEA) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 5) && INST_REG(2) == REG_E) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xEB) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 5) && INST_REG(2) == REG_H) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xEC) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 5) && INST_REG(2) == REG_L) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xED) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 6) && INST_REG(2) == REG_A) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xF7) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 6) && INST_REG(2) == REG_B) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xF0) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 6) && INST_REG(2) == REG_C) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xF1) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 6) && INST_REG(2) == REG_D) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xF2) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 6) && INST_REG(2) == REG_E) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xF3) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 6) && INST_REG(2) == REG_H) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xF4) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 6) && INST_REG(2) == REG_L) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xF5) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 7) && INST_REG(2) == REG_A) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xFF) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 7) && INST_REG(2) == REG_B) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xF8) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 7) && INST_REG(2) == REG_C) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xF9) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 7) && INST_REG(2) == REG_D) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xFA) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 7) && INST_REG(2) == REG_E) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xFB) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 7) && INST_REG(2) == REG_H) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xFC) | |||||
| if ((INST_IMM(0).mask & IMM_BIT && INST_IMM(0).uval == 7) && INST_REG(2) == REG_L) | |||||
| INST_RETURN(4, INST_INDEX_PREFIX(1), 0xCB, INST_INDEX(1).offset, 0xFD) | |||||
| INST_ERROR(ARG_VALUE) | |||||
| } | |||||
| INST_ERROR(ARG_TYPE) | |||||
| } | |||||
| /* @AUTOGEN_INST_BLOCK_END */ | /* @AUTOGEN_INST_BLOCK_END */ | ||||
| /* | /* | ||||
| @@ -1421,6 +2029,9 @@ static ASMInstParser lookup_parser(uint32_t key) | |||||
| HANDLE(out) | HANDLE(out) | ||||
| HANDLE(outd) | HANDLE(outd) | ||||
| HANDLE(outi) | HANDLE(outi) | ||||
| HANDLE(pop) | |||||
| HANDLE(push) | |||||
| HANDLE(res) | |||||
| HANDLE(reti) | HANDLE(reti) | ||||
| HANDLE(retn) | HANDLE(retn) | ||||
| HANDLE(rla) | HANDLE(rla) | ||||
| @@ -1429,6 +2040,7 @@ static ASMInstParser lookup_parser(uint32_t key) | |||||
| HANDLE(rra) | HANDLE(rra) | ||||
| HANDLE(rrca) | HANDLE(rrca) | ||||
| HANDLE(scf) | HANDLE(scf) | ||||
| HANDLE(set) | |||||
| /* @AUTOGEN_LOOKUP_BLOCK_END */ | /* @AUTOGEN_LOOKUP_BLOCK_END */ | ||||
| return NULL; | return NULL; | ||||
| } | } | ||||
+ 524
- 12
src/assembler/instructions.yml
View File
| @@ -832,17 +832,283 @@ outi: | |||||
| args: no | args: no | ||||
| return: [0xED, 0xA3] | return: [0xED, 0xA3] | ||||
| # pop: | |||||
| # args: yes | |||||
| # return: TODO | |||||
| pop: | |||||
| args: yes | |||||
| cases: | |||||
| - type: [register] | |||||
| cases: | |||||
| - cond: [bc] | |||||
| return: [0xC1] | |||||
| - cond: [de] | |||||
| return: [0xD1] | |||||
| - cond: [hl|i] | |||||
| return: [0xE1] | |||||
| - cond: [af] | |||||
| return: [0xF1] | |||||
| # push: | |||||
| # args: yes | |||||
| # return: TODO | |||||
| push: | |||||
| args: yes | |||||
| cases: | |||||
| - type: [register] | |||||
| cases: | |||||
| - cond: [bc] | |||||
| return: [0xC5] | |||||
| - cond: [de] | |||||
| return: [0xD5] | |||||
| - cond: [hl|i] | |||||
| return: [0xE5] | |||||
| - cond: [af] | |||||
| return: [0xF5] | |||||
| # res: | |||||
| # args: yes | |||||
| # return: TODO | |||||
| res: | |||||
| args: yes | |||||
| cases: | |||||
| - type: [immediate, register] | |||||
| cases: | |||||
| - cond: [bit.0, a] | |||||
| return: [0xCB, 0x87] | |||||
| - cond: [bit.0, b] | |||||
| return: [0xCB, 0x80] | |||||
| - cond: [bit.0, c] | |||||
| return: [0xCB, 0x81] | |||||
| - cond: [bit.0, d] | |||||
| return: [0xCB, 0x82] | |||||
| - cond: [bit.0, e] | |||||
| return: [0xCB, 0x83] | |||||
| - cond: [bit.0, h] | |||||
| return: [0xCB, 0x84] | |||||
| - cond: [bit.0, l] | |||||
| return: [0xCB, 0x85] | |||||
| - cond: [bit.1, a] | |||||
| return: [0xCB, 0x8F] | |||||
| - cond: [bit.1, b] | |||||
| return: [0xCB, 0x88] | |||||
| - cond: [bit.1, c] | |||||
| return: [0xCB, 0x89] | |||||
| - cond: [bit.1, d] | |||||
| return: [0xCB, 0x8A] | |||||
| - cond: [bit.1, e] | |||||
| return: [0xCB, 0x8B] | |||||
| - cond: [bit.1, h] | |||||
| return: [0xCB, 0x8C] | |||||
| - cond: [bit.1, l] | |||||
| return: [0xCB, 0x8D] | |||||
| - cond: [bit.2, a] | |||||
| return: [0xCB, 0x97] | |||||
| - cond: [bit.2, b] | |||||
| return: [0xCB, 0x90] | |||||
| - cond: [bit.2, c] | |||||
| return: [0xCB, 0x91] | |||||
| - cond: [bit.2, d] | |||||
| return: [0xCB, 0x92] | |||||
| - cond: [bit.2, e] | |||||
| return: [0xCB, 0x93] | |||||
| - cond: [bit.2, h] | |||||
| return: [0xCB, 0x94] | |||||
| - cond: [bit.2, l] | |||||
| return: [0xCB, 0x95] | |||||
| - cond: [bit.3, a] | |||||
| return: [0xCB, 0x9F] | |||||
| - cond: [bit.3, b] | |||||
| return: [0xCB, 0x98] | |||||
| - cond: [bit.3, c] | |||||
| return: [0xCB, 0x99] | |||||
| - cond: [bit.3, d] | |||||
| return: [0xCB, 0x9A] | |||||
| - cond: [bit.3, e] | |||||
| return: [0xCB, 0x9B] | |||||
| - cond: [bit.3, h] | |||||
| return: [0xCB, 0x9C] | |||||
| - cond: [bit.3, l] | |||||
| return: [0xCB, 0x9D] | |||||
| - cond: [bit.4, a] | |||||
| return: [0xCB, 0xA7] | |||||
| - cond: [bit.4, b] | |||||
| return: [0xCB, 0xA0] | |||||
| - cond: [bit.4, c] | |||||
| return: [0xCB, 0xA1] | |||||
| - cond: [bit.4, d] | |||||
| return: [0xCB, 0xA2] | |||||
| - cond: [bit.4, e] | |||||
| return: [0xCB, 0xA3] | |||||
| - cond: [bit.4, h] | |||||
| return: [0xCB, 0xA4] | |||||
| - cond: [bit.4, l] | |||||
| return: [0xCB, 0xA5] | |||||
| - cond: [bit.5, a] | |||||
| return: [0xCB, 0xAF] | |||||
| - cond: [bit.5, b] | |||||
| return: [0xCB, 0xA8] | |||||
| - cond: [bit.5, c] | |||||
| return: [0xCB, 0xA9] | |||||
| - cond: [bit.5, d] | |||||
| return: [0xCB, 0xAA] | |||||
| - cond: [bit.5, e] | |||||
| return: [0xCB, 0xAB] | |||||
| - cond: [bit.5, h] | |||||
| return: [0xCB, 0xAC] | |||||
| - cond: [bit.5, l] | |||||
| return: [0xCB, 0xAD] | |||||
| - cond: [bit.6, a] | |||||
| return: [0xCB, 0xB7] | |||||
| - cond: [bit.6, b] | |||||
| return: [0xCB, 0xB0] | |||||
| - cond: [bit.6, c] | |||||
| return: [0xCB, 0xB1] | |||||
| - cond: [bit.6, d] | |||||
| return: [0xCB, 0xB2] | |||||
| - cond: [bit.6, e] | |||||
| return: [0xCB, 0xB3] | |||||
| - cond: [bit.6, h] | |||||
| return: [0xCB, 0xB4] | |||||
| - cond: [bit.6, l] | |||||
| return: [0xCB, 0xB5] | |||||
| - cond: [bit.7, a] | |||||
| return: [0xCB, 0xBF] | |||||
| - cond: [bit.7, b] | |||||
| return: [0xCB, 0xB8] | |||||
| - cond: [bit.7, c] | |||||
| return: [0xCB, 0xB9] | |||||
| - cond: [bit.7, d] | |||||
| return: [0xCB, 0xBA] | |||||
| - cond: [bit.7, e] | |||||
| return: [0xCB, 0xBB] | |||||
| - cond: [bit.7, h] | |||||
| return: [0xCB, 0xBC] | |||||
| - cond: [bit.7, l] | |||||
| return: [0xCB, 0xBD] | |||||
| - type: [immediate, indirect_hl_or_indexed] | |||||
| cases: | |||||
| - cond: [bit.0, _] | |||||
| return: [0xCB, 0x86] | |||||
| - cond: [bit.1, _] | |||||
| return: [0xCB, 0x8E] | |||||
| - cond: [bit.2, _] | |||||
| return: [0xCB, 0x96] | |||||
| - cond: [bit.3, _] | |||||
| return: [0xCB, 0x9E] | |||||
| - cond: [bit.4, _] | |||||
| return: [0xCB, 0xA6] | |||||
| - cond: [bit.5, _] | |||||
| return: [0xCB, 0xAE] | |||||
| - cond: [bit.6, _] | |||||
| return: [0xCB, 0xB6] | |||||
| - cond: [bit.7, _] | |||||
| return: [0xCB, 0xBE] | |||||
| - type: [immediate, indexed, register] | |||||
| cases: | |||||
| - cond: [bit.0, _, a] | |||||
| return: [0xCB, 0x87] | |||||
| - cond: [bit.0, _, b] | |||||
| return: [0xCB, 0x80] | |||||
| - cond: [bit.0, _, c] | |||||
| return: [0xCB, 0x81] | |||||
| - cond: [bit.0, _, d] | |||||
| return: [0xCB, 0x82] | |||||
| - cond: [bit.0, _, e] | |||||
| return: [0xCB, 0x83] | |||||
| - cond: [bit.0, _, h] | |||||
| return: [0xCB, 0x84] | |||||
| - cond: [bit.0, _, l] | |||||
| return: [0xCB, 0x85] | |||||
| - cond: [bit.1, _, a] | |||||
| return: [0xCB, 0x8F] | |||||
| - cond: [bit.1, _, b] | |||||
| return: [0xCB, 0x88] | |||||
| - cond: [bit.1, _, c] | |||||
| return: [0xCB, 0x89] | |||||
| - cond: [bit.1, _, d] | |||||
| return: [0xCB, 0x8A] | |||||
| - cond: [bit.1, _, e] | |||||
| return: [0xCB, 0x8B] | |||||
| - cond: [bit.1, _, h] | |||||
| return: [0xCB, 0x8C] | |||||
| - cond: [bit.1, _, l] | |||||
| return: [0xCB, 0x8D] | |||||
| - cond: [bit.2, _, a] | |||||
| return: [0xCB, 0x97] | |||||
| - cond: [bit.2, _, b] | |||||
| return: [0xCB, 0x90] | |||||
| - cond: [bit.2, _, c] | |||||
| return: [0xCB, 0x91] | |||||
| - cond: [bit.2, _, d] | |||||
| return: [0xCB, 0x92] | |||||
| - cond: [bit.2, _, e] | |||||
| return: [0xCB, 0x93] | |||||
| - cond: [bit.2, _, h] | |||||
| return: [0xCB, 0x94] | |||||
| - cond: [bit.2, _, l] | |||||
| return: [0xCB, 0x95] | |||||
| - cond: [bit.3, _, a] | |||||
| return: [0xCB, 0x9F] | |||||
| - cond: [bit.3, _, b] | |||||
| return: [0xCB, 0x98] | |||||
| - cond: [bit.3, _, c] | |||||
| return: [0xCB, 0x99] | |||||
| - cond: [bit.3, _, d] | |||||
| return: [0xCB, 0x9A] | |||||
| - cond: [bit.3, _, e] | |||||
| return: [0xCB, 0x9B] | |||||
| - cond: [bit.3, _, h] | |||||
| return: [0xCB, 0x9C] | |||||
| - cond: [bit.3, _, l] | |||||
| return: [0xCB, 0x9D] | |||||
| - cond: [bit.4, _, a] | |||||
| return: [0xCB, 0xA7] | |||||
| - cond: [bit.4, _, b] | |||||
| return: [0xCB, 0xA0] | |||||
| - cond: [bit.4, _, c] | |||||
| return: [0xCB, 0xA1] | |||||
| - cond: [bit.4, _, d] | |||||
| return: [0xCB, 0xA2] | |||||
| - cond: [bit.4, _, e] | |||||
| return: [0xCB, 0xA3] | |||||
| - cond: [bit.4, _, h] | |||||
| return: [0xCB, 0xA4] | |||||
| - cond: [bit.4, _, l] | |||||
| return: [0xCB, 0xA5] | |||||
| - cond: [bit.5, _, a] | |||||
| return: [0xCB, 0xAF] | |||||
| - cond: [bit.5, _, b] | |||||
| return: [0xCB, 0xA8] | |||||
| - cond: [bit.5, _, c] | |||||
| return: [0xCB, 0xA9] | |||||
| - cond: [bit.5, _, d] | |||||
| return: [0xCB, 0xAA] | |||||
| - cond: [bit.5, _, e] | |||||
| return: [0xCB, 0xAB] | |||||
| - cond: [bit.5, _, h] | |||||
| return: [0xCB, 0xAC] | |||||
| - cond: [bit.5, _, l] | |||||
| return: [0xCB, 0xAD] | |||||
| - cond: [bit.6, _, a] | |||||
| return: [0xCB, 0xB7] | |||||
| - cond: [bit.6, _, b] | |||||
| return: [0xCB, 0xB0] | |||||
| - cond: [bit.6, _, c] | |||||
| return: [0xCB, 0xB1] | |||||
| - cond: [bit.6, _, d] | |||||
| return: [0xCB, 0xB2] | |||||
| - cond: [bit.6, _, e] | |||||
| return: [0xCB, 0xB3] | |||||
| - cond: [bit.6, _, h] | |||||
| return: [0xCB, 0xB4] | |||||
| - cond: [bit.6, _, l] | |||||
| return: [0xCB, 0xB5] | |||||
| - cond: [bit.7, _, a] | |||||
| return: [0xCB, 0xBF] | |||||
| - cond: [bit.7, _, b] | |||||
| return: [0xCB, 0xB8] | |||||
| - cond: [bit.7, _, c] | |||||
| return: [0xCB, 0xB9] | |||||
| - cond: [bit.7, _, d] | |||||
| return: [0xCB, 0xBA] | |||||
| - cond: [bit.7, _, e] | |||||
| return: [0xCB, 0xBB] | |||||
| - cond: [bit.7, _, h] | |||||
| return: [0xCB, 0xBC] | |||||
| - cond: [bit.7, _, l] | |||||
| return: [0xCB, 0xBD] | |||||
| # ret: | # ret: | ||||
| # args: yes | # args: yes | ||||
| @@ -908,9 +1174,255 @@ scf: | |||||
| args: no | args: no | ||||
| return: [0x37] | return: [0x37] | ||||
| # set: | |||||
| # args: yes | |||||
| # return: TODO | |||||
| set: | |||||
| args: yes | |||||
| cases: | |||||
| - type: [immediate, register] | |||||
| cases: | |||||
| - cond: [bit.0, a] | |||||
| return: [0xCB, 0xC7] | |||||
| - cond: [bit.0, b] | |||||
| return: [0xCB, 0xC0] | |||||
| - cond: [bit.0, c] | |||||
| return: [0xCB, 0xC1] | |||||
| - cond: [bit.0, d] | |||||
| return: [0xCB, 0xC2] | |||||
| - cond: [bit.0, e] | |||||
| return: [0xCB, 0xC3] | |||||
| - cond: [bit.0, h] | |||||
| return: [0xCB, 0xC4] | |||||
| - cond: [bit.0, l] | |||||
| return: [0xCB, 0xC5] | |||||
| - cond: [bit.1, a] | |||||
| return: [0xCB, 0xCF] | |||||
| - cond: [bit.1, b] | |||||
| return: [0xCB, 0xC8] | |||||
| - cond: [bit.1, c] | |||||
| return: [0xCB, 0xC9] | |||||
| - cond: [bit.1, d] | |||||
| return: [0xCB, 0xCA] | |||||
| - cond: [bit.1, e] | |||||
| return: [0xCB, 0xCB] | |||||
| - cond: [bit.1, h] | |||||
| return: [0xCB, 0xCC] | |||||
| - cond: [bit.1, l] | |||||
| return: [0xCB, 0xCD] | |||||
| - cond: [bit.2, a] | |||||
| return: [0xCB, 0xD7] | |||||
| - cond: [bit.2, b] | |||||
| return: [0xCB, 0xD0] | |||||
| - cond: [bit.2, c] | |||||
| return: [0xCB, 0xD1] | |||||
| - cond: [bit.2, d] | |||||
| return: [0xCB, 0xD2] | |||||
| - cond: [bit.2, e] | |||||
| return: [0xCB, 0xD3] | |||||
| - cond: [bit.2, h] | |||||
| return: [0xCB, 0xD4] | |||||
| - cond: [bit.2, l] | |||||
| return: [0xCB, 0xD5] | |||||
| - cond: [bit.3, a] | |||||
| return: [0xCB, 0xDF] | |||||
| - cond: [bit.3, b] | |||||
| return: [0xCB, 0xD8] | |||||
| - cond: [bit.3, c] | |||||
| return: [0xCB, 0xD9] | |||||
| - cond: [bit.3, d] | |||||
| return: [0xCB, 0xDA] | |||||
| - cond: [bit.3, e] | |||||
| return: [0xCB, 0xDB] | |||||
| - cond: [bit.3, h] | |||||
| return: [0xCB, 0xDC] | |||||
| - cond: [bit.3, l] | |||||
| return: [0xCB, 0xDD] | |||||
| - cond: [bit.4, a] | |||||
| return: [0xCB, 0xE7] | |||||
| - cond: [bit.4, b] | |||||
| return: [0xCB, 0xE0] | |||||
| - cond: [bit.4, c] | |||||
| return: [0xCB, 0xE1] | |||||
| - cond: [bit.4, d] | |||||
| return: [0xCB, 0xE2] | |||||
| - cond: [bit.4, e] | |||||
| return: [0xCB, 0xE3] | |||||
| - cond: [bit.4, h] | |||||
| return: [0xCB, 0xE4] | |||||
| - cond: [bit.4, l] | |||||
| return: [0xCB, 0xE5] | |||||
| - cond: [bit.5, a] | |||||
| return: [0xCB, 0xEF] | |||||
| - cond: [bit.5, b] | |||||
| return: [0xCB, 0xE8] | |||||
| - cond: [bit.5, c] | |||||
| return: [0xCB, 0xE9] | |||||
| - cond: [bit.5, d] | |||||
| return: [0xCB, 0xEA] | |||||
| - cond: [bit.5, e] | |||||
| return: [0xCB, 0xEB] | |||||
| - cond: [bit.5, h] | |||||
| return: [0xCB, 0xEC] | |||||
| - cond: [bit.5, l] | |||||
| return: [0xCB, 0xED] | |||||
| - cond: [bit.6, a] | |||||
| return: [0xCB, 0xF7] | |||||
| - cond: [bit.6, b] | |||||
| return: [0xCB, 0xF0] | |||||
| - cond: [bit.6, c] | |||||
| return: [0xCB, 0xF1] | |||||
| - cond: [bit.6, d] | |||||
| return: [0xCB, 0xF2] | |||||
| - cond: [bit.6, e] | |||||
| return: [0xCB, 0xF3] | |||||
| - cond: [bit.6, h] | |||||
| return: [0xCB, 0xF4] | |||||
| - cond: [bit.6, l] | |||||
| return: [0xCB, 0xF5] | |||||
| - cond: [bit.7, a] | |||||
| return: [0xCB, 0xFF] | |||||
| - cond: [bit.7, b] | |||||
| return: [0xCB, 0xF8] | |||||
| - cond: [bit.7, c] | |||||
| return: [0xCB, 0xF9] | |||||
| - cond: [bit.7, d] | |||||
| return: [0xCB, 0xFA] | |||||
| - cond: [bit.7, e] | |||||
| return: [0xCB, 0xFB] | |||||
| - cond: [bit.7, h] | |||||
| return: [0xCB, 0xFC] | |||||
| - cond: [bit.7, l] | |||||
| return: [0xCB, 0xFD] | |||||
| - type: [immediate, indirect_hl_or_indexed] | |||||
| cases: | |||||
| - cond: [bit.0, _] | |||||
| return: [0xCB, 0xC6] | |||||
| - cond: [bit.1, _] | |||||
| return: [0xCB, 0xCE] | |||||
| - cond: [bit.2, _] | |||||
| return: [0xCB, 0xD6] | |||||
| - cond: [bit.3, _] | |||||
| return: [0xCB, 0xDE] | |||||
| - cond: [bit.4, _] | |||||
| return: [0xCB, 0xE6] | |||||
| - cond: [bit.5, _] | |||||
| return: [0xCB, 0xEE] | |||||
| - cond: [bit.6, _] | |||||
| return: [0xCB, 0xF6] | |||||
| - cond: [bit.7, _] | |||||
| return: [0xCB, 0xFE] | |||||
| - type: [immediate, indexed, register] | |||||
| cases: | |||||
| - cond: [bit.0, _, a] | |||||
| return: [0xCB, 0xC7] | |||||
| - cond: [bit.0, _, b] | |||||
| return: [0xCB, 0xC0] | |||||
| - cond: [bit.0, _, c] | |||||
| return: [0xCB, 0xC1] | |||||
| - cond: [bit.0, _, d] | |||||
| return: [0xCB, 0xC2] | |||||
| - cond: [bit.0, _, e] | |||||
| return: [0xCB, 0xC3] | |||||
| - cond: [bit.0, _, h] | |||||
| return: [0xCB, 0xC4] | |||||
| - cond: [bit.0, _, l] | |||||
| return: [0xCB, 0xC5] | |||||
| - cond: [bit.1, _, a] | |||||
| return: [0xCB, 0xCF] | |||||
| - cond: [bit.1, _, b] | |||||
| return: [0xCB, 0xC8] | |||||
| - cond: [bit.1, _, c] | |||||
| return: [0xCB, 0xC9] | |||||
| - cond: [bit.1, _, d] | |||||
| return: [0xCB, 0xCA] | |||||
| - cond: [bit.1, _, e] | |||||
| return: [0xCB, 0xCB] | |||||
| - cond: [bit.1, _, h] | |||||
| return: [0xCB, 0xCC] | |||||
| - cond: [bit.1, _, l] | |||||
| return: [0xCB, 0xCD] | |||||
| - cond: [bit.2, _, a] | |||||
| return: [0xCB, 0xD7] | |||||
| - cond: [bit.2, _, b] | |||||
| return: [0xCB, 0xD0] | |||||
| - cond: [bit.2, _, c] | |||||
| return: [0xCB, 0xD1] | |||||
| - cond: [bit.2, _, d] | |||||
| return: [0xCB, 0xD2] | |||||
| - cond: [bit.2, _, e] | |||||
| return: [0xCB, 0xD3] | |||||
| - cond: [bit.2, _, h] | |||||
| return: [0xCB, 0xD4] | |||||
| - cond: [bit.2, _, l] | |||||
| return: [0xCB, 0xD5] | |||||
| - cond: [bit.3, _, a] | |||||
| return: [0xCB, 0xDF] | |||||
| - cond: [bit.3, _, b] | |||||
| return: [0xCB, 0xD8] | |||||
| - cond: [bit.3, _, c] | |||||
| return: [0xCB, 0xD9] | |||||
| - cond: [bit.3, _, d] | |||||
| return: [0xCB, 0xDA] | |||||
| - cond: [bit.3, _, e] | |||||
| return: [0xCB, 0xDB] | |||||
| - cond: [bit.3, _, h] | |||||
| return: [0xCB, 0xDC] | |||||
| - cond: [bit.3, _, l] | |||||
| return: [0xCB, 0xDD] | |||||
| - cond: [bit.4, _, a] | |||||
| return: [0xCB, 0xE7] | |||||
| - cond: [bit.4, _, b] | |||||
| return: [0xCB, 0xE0] | |||||
| - cond: [bit.4, _, c] | |||||
| return: [0xCB, 0xE1] | |||||
| - cond: [bit.4, _, d] | |||||
| return: [0xCB, 0xE2] | |||||
| - cond: [bit.4, _, e] | |||||
| return: [0xCB, 0xE3] | |||||
| - cond: [bit.4, _, h] | |||||
| return: [0xCB, 0xE4] | |||||
| - cond: [bit.4, _, l] | |||||
| return: [0xCB, 0xE5] | |||||
| - cond: [bit.5, _, a] | |||||
| return: [0xCB, 0xEF] | |||||
| - cond: [bit.5, _, b] | |||||
| return: [0xCB, 0xE8] | |||||
| - cond: [bit.5, _, c] | |||||
| return: [0xCB, 0xE9] | |||||
| - cond: [bit.5, _, d] | |||||
| return: [0xCB, 0xEA] | |||||
| - cond: [bit.5, _, e] | |||||
| return: [0xCB, 0xEB] | |||||
| - cond: [bit.5, _, h] | |||||
| return: [0xCB, 0xEC] | |||||
| - cond: [bit.5, _, l] | |||||
| return: [0xCB, 0xED] | |||||
| - cond: [bit.6, _, a] | |||||
| return: [0xCB, 0xF7] | |||||
| - cond: [bit.6, _, b] | |||||
| return: [0xCB, 0xF0] | |||||
| - cond: [bit.6, _, c] | |||||
| return: [0xCB, 0xF1] | |||||
| - cond: [bit.6, _, d] | |||||
| return: [0xCB, 0xF2] | |||||
| - cond: [bit.6, _, e] | |||||
| return: [0xCB, 0xF3] | |||||
| - cond: [bit.6, _, h] | |||||
| return: [0xCB, 0xF4] | |||||
| - cond: [bit.6, _, l] | |||||
| return: [0xCB, 0xF5] | |||||
| - cond: [bit.7, _, a] | |||||
| return: [0xCB, 0xFF] | |||||
| - cond: [bit.7, _, b] | |||||
| return: [0xCB, 0xF8] | |||||
| - cond: [bit.7, _, c] | |||||
| return: [0xCB, 0xF9] | |||||
| - cond: [bit.7, _, d] | |||||
| return: [0xCB, 0xFA] | |||||
| - cond: [bit.7, _, e] | |||||
| return: [0xCB, 0xFB] | |||||
| - cond: [bit.7, _, h] | |||||
| return: [0xCB, 0xFC] | |||||
| - cond: [bit.7, _, l] | |||||
| return: [0xCB, 0xFD] | |||||
| # sl1: | # sl1: | ||||
| # args: yes | # args: yes | ||||