An emulator, assembler, and disassembler for the Sega Game Gear
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  1. /* Copyright (C) 2014-2016 Ben Kurtovic <ben.kurtovic@gmail.com>
  2. Released under the terms of the MIT License. See LICENSE for details. */
  3. #include <string.h>
  4. #include "vdp.h"
  5. #include "util.h"
  6. #define CODE_VRAM_READ 0
  7. #define CODE_VRAM_WRITE 1
  8. #define CODE_REG_WRITE 2
  9. #define CODE_CRAM_WRITE 3
  10. /*
  11. Initialize the Video Display Processor (VDP).
  12. */
  13. void vdp_init(VDP *vdp)
  14. {
  15. vdp->vram = cr_malloc(sizeof(uint8_t) * VDP_VRAM_SIZE);
  16. vdp->cram = cr_malloc(sizeof(uint8_t) * VDP_CRAM_SIZE);
  17. memset(vdp->vram, 0x00, VDP_VRAM_SIZE);
  18. memset(vdp->cram, 0x00, VDP_CRAM_SIZE);
  19. }
  20. /*
  21. Free memory previously allocated by the VDP.
  22. */
  23. void vdp_free(VDP *vdp)
  24. {
  25. free(vdp->vram);
  26. }
  27. /*
  28. Power on the VDP, setting up initial state.
  29. */
  30. void vdp_power(VDP *vdp)
  31. {
  32. vdp->regs[0x00] = 0x00;
  33. vdp->regs[0x01] = 0x00;
  34. vdp->regs[0x02] = 0xFF;
  35. vdp->regs[0x03] = 0xFF;
  36. vdp->regs[0x04] = 0xFF;
  37. vdp->regs[0x05] = 0xFF;
  38. vdp->regs[0x06] = 0xFF;
  39. vdp->regs[0x07] = 0x00;
  40. vdp->regs[0x08] = 0x00;
  41. vdp->regs[0x09] = 0x00;
  42. vdp->regs[0x0A] = 0x01;
  43. vdp->h_counter = 0;
  44. vdp->v_counter = 0;
  45. vdp->v_count_jump = false;
  46. vdp->control_code = 0;
  47. vdp->control_addr = 0;
  48. vdp->control_flag = false;
  49. vdp->stat_int = vdp->stat_ovf = vdp->stat_col = 0;
  50. vdp->read_buf = 0;
  51. vdp->cram_latch = 0;
  52. }
  53. /*
  54. Return the base address of the pattern name table.
  55. */
  56. static uint16_t get_pnt_base(const VDP *vdp)
  57. {
  58. return (vdp->regs[0x02] & 0x0E) << 10;
  59. }
  60. /*
  61. Return the base address of the sprite attribute table.
  62. */
  63. static uint16_t get_sat_base(const VDP *vdp)
  64. {
  65. return (vdp->regs[0x05] & 0x7E) << 7;
  66. }
  67. /*
  68. Return the base address of the sprite generator table.
  69. */
  70. static uint16_t get_sgt_base(const VDP *vdp)
  71. {
  72. return (vdp->regs[0x06] & 0x04) << 11;
  73. }
  74. /*
  75. Return the CRAM address of the backdrop color.
  76. */
  77. static uint8_t get_backdrop_addr(const VDP *vdp)
  78. {
  79. return ((vdp->regs[0x07] & 0x0F) << 1) + 0x20;
  80. }
  81. /*
  82. Advance the V counter for the next scanline.
  83. */
  84. static void advance_scanline(VDP *vdp)
  85. {
  86. if (vdp->v_counter == 0xDA)
  87. vdp->v_count_jump = !vdp->v_count_jump;
  88. if (vdp->v_counter == 0xDA && vdp->v_count_jump)
  89. vdp->v_counter = 0xD5;
  90. else
  91. vdp->v_counter++;
  92. }
  93. /*
  94. Simulate one scanline within the VDP.
  95. TODO: elaborate
  96. */
  97. void vdp_simulate_line(VDP *vdp)
  98. {
  99. if (vdp->v_counter >= 0x18 && vdp->v_counter < 0xA8) {
  100. // TODO: draw current line
  101. }
  102. // TODO: if (...) IRQ
  103. advance_scanline(vdp);
  104. }
  105. /*
  106. Read a byte from the VDP's control port, revealing status flags.
  107. The status byte consists of:
  108. 7 6 5 4 3 2 1 0
  109. F 9S C * * * * *
  110. - F: Interrupt flag: set when the effective display area is completed
  111. - 9S: 9th sprite / Sprite overflow: more than eight sprites on a scanline
  112. - C: Collision flag: two sprites have an overlapping pixel
  113. - *: Unused
  114. The control flag is also reset.
  115. */
  116. uint8_t vdp_read_control(VDP *vdp)
  117. {
  118. uint8_t status =
  119. (vdp->stat_int << 8) + (vdp->stat_ovf << 7) + (vdp->stat_col << 6);
  120. vdp->stat_int = vdp->stat_ovf = vdp->stat_col = 0;
  121. vdp->control_flag = false;
  122. return status;
  123. }
  124. /*
  125. Read a byte from the VDP's data port.
  126. This will return the contents of the read buffer, and then fill the buffer
  127. with the VRAM at the current control address, before incrementing the
  128. control address. The control flag is also reset.
  129. */
  130. uint8_t vdp_read_data(VDP *vdp)
  131. {
  132. uint8_t buffer = vdp->read_buf;
  133. vdp->read_buf = vdp->vram[vdp->control_addr];
  134. vdp->control_addr = (vdp->control_addr + 1) % 0x3FFF;
  135. vdp->control_flag = false;
  136. return buffer;
  137. }
  138. /*
  139. Write a byte into the VDP's control port.
  140. Depending on the status of the control flag, this will either update the
  141. lower byte of the control address, or the upper six bits of the control
  142. address and the control code. The flag is toggled by each control write,
  143. and reset by each control read and data read or write.
  144. If the control code indicates a VRAM read, the read buffer will be filled
  145. with the VRAM at the given control address, which is then incremented. If
  146. the code indicates a register write, the corresponding register
  147. (byte & 0x0F) will be written with the lower byte of the control address.
  148. */
  149. void vdp_write_control(VDP *vdp, uint8_t byte)
  150. {
  151. if (!vdp->control_flag) { // First byte
  152. vdp->control_addr = (vdp->control_addr & 0x3F00) + byte;
  153. } else { // Second byte
  154. vdp->control_addr = ((byte & 0x3F) << 8) + (vdp->control_addr & 0xFF);
  155. vdp->control_code = byte >> 6;
  156. }
  157. if (vdp->control_code == CODE_VRAM_READ) {
  158. vdp->read_buf = vdp->vram[vdp->control_addr];
  159. vdp->control_addr = (vdp->control_addr + 1) % 0x3FFF;
  160. } else if (vdp->control_code == CODE_REG_WRITE) {
  161. uint8_t reg = byte & 0x0F;
  162. if (reg <= VDP_REGS)
  163. vdp->regs[reg] = vdp->control_addr & 0xFF;
  164. }
  165. vdp->control_flag = !vdp->control_flag;
  166. }
  167. /*
  168. Write a byte into CRAM. Handles even/odd address latching.
  169. */
  170. static void write_cram(VDP *vdp, uint8_t byte)
  171. {
  172. if (!(vdp->control_addr % 2)) {
  173. vdp->cram_latch = byte;
  174. } else {
  175. vdp->cram[(vdp->control_addr - 1) % 0x3F] = vdp->cram_latch;
  176. vdp->cram[ vdp->control_addr % 0x3F] = byte % 0x0F;
  177. }
  178. }
  179. /*
  180. Write a byte into the VDP's data port.
  181. Depending on the control code, this either writes into the VRAM or CRAM at
  182. the current control address, which is then incremented. The control flag is
  183. also reset, and the read buffer is squashed.
  184. */
  185. void vdp_write_data(VDP *vdp, uint8_t byte)
  186. {
  187. if (vdp->control_code == CODE_CRAM_WRITE)
  188. write_cram(vdp, byte);
  189. else
  190. vdp->vram[vdp->control_addr] = byte;
  191. vdp->control_addr = (vdp->control_addr + 1) % 0x3FFF;
  192. vdp->control_flag = false;
  193. vdp->read_buf = byte;
  194. }
  195. /*
  196. @DEBUG_LEVEL
  197. Print out all register values to stdout.
  198. */
  199. void vdp_dump_registers(const VDP *vdp)
  200. {
  201. const uint8_t *regs = vdp->regs;
  202. DEBUG("Dumping VDP register values:")
  203. DEBUG("- $00: 0x%02X (" BINARY_FMT ")", regs[0x00], BINARY_VAL(regs[0]))
  204. DEBUG("- $01: 0x%02X (" BINARY_FMT ")", regs[0x01], BINARY_VAL(regs[1]))
  205. DEBUG("- $02: 0x%02X (PNT: 0x%04X)", regs[0x02], get_pnt_base(vdp))
  206. DEBUG("- $03: 0x%02X (CT)", regs[0x03])
  207. DEBUG("- $04: 0x%02X (BPG)", regs[0x04])
  208. DEBUG("- $05: 0x%02X (SAT: 0x%04X)", regs[0x05], get_sat_base(vdp))
  209. DEBUG("- $06: 0x%02X (SGT: 0x%04X)", regs[0x06], get_sgt_base(vdp))
  210. DEBUG("- $07: 0x%02X (BDC: 0x%02X)", regs[0x07], get_backdrop_addr(vdp))
  211. DEBUG("- $08: 0x%02X (HS)", regs[0x08])
  212. DEBUG("- $09: 0x%02X (VS)", regs[0x09])
  213. DEBUG("- $0A: 0x%02X (LC)", regs[0x0A])
  214. }